In semiconductor storage devices such as an EEPROM (electrically erasable programmable read-only memory), a boosted voltage (such as 6V) obtained by boosting a supply voltage Vcc (such as 1.8V) supplied to the external power supply terminal by a boost circuit (boost converter) provided inside the semiconductor storage device is supplied as a driving power supply (also referred to as a “word line driving power supply”) for a word driver that drives a word line. The word driver drives a word line selected by an X decoder that decodes an input X address to the boosted potential.
FIG. 6 is a diagram showing a typical example of a configuration of supplying a boosted voltage Vword (word line supply potential) to a power supply line that supplies a driving power supply to the word driver (that will be referred to as a “word line driving power supply line” in this specification). Referring to FIG. 6, a word line driving power supply line 22 is connected as a power supply for a plurality of word drivers not shown, and a voltage (such as 6V) obtained by boosting an external supply voltage Vcc (such as 1.8V) by a boost circuit 20 is supplied to the word line driving power supply line 22. A stabilizing capacitor 21 is connected to this word line driving power supply line 22.
FIG. 7 is a diagram schematically illustrating a typical configuration of the boost circuit 20 in FIG. 6. Referring to FIG. 7, the boost circuit 20 makes a voltage comparison between a voltage obtained by division of the output voltage of the boost circuit 20 by voltage-dividing resistors 2021 and 2022 and a reference voltage Vref using a comparison circuit 203, for example. When the output voltage of the boost circuit 20 is reduced to be equal to or less than the reference voltage Vref, the boost circuit 20 controls an oscillator (OSC) 204 such as a ring oscillator to start oscillation based on an output signal from the comparison circuit 203 indicating the result of comparison, and then to supply an oscillation clock to a charge pump 201. Then, the charge pump 201 stores electric charge in a capacitor thereof (not shown) for performing a voltage boosting operation, and stores the electric charge in an output smoothing capacitor (not shown).
By the way, in the EEPROM to be subjected to standby control, no read access is performed when the EEPROM is in a standby state, so that the word drivers are not activated. More specifically when the EEPROM is in the standby state, no word line is selected, so that it does not happen that a word driver drives a word line. For this reason, when the EEPROM is in the standby state, the voltage boosting operation of the boost circuit 20 is stopped (however, the word line driving power supply line is kept at a potential of 6V, for example).
The EEPROM is mounted on electronic devices such as cell phones, digital cameras, cell phones with cameras, and PDAs (Personal Digital Assistants) as a nonvolatile memory. Lower power consumption is demanded for battery-driving type cell phones, so that lower power consumption of the boost circuit in the standby state is demanded.
When the combined series resistance of the resistors 2021 and 2022 is indicated by R, and a current that flows through the voltage dividing resistors 2021 and 2022 is indicated by I in the boost circuit 20 in FIG. 7, for example, I=V/R holds. Since power (electric power) is expressed by an equation of VI=V2/R. Thus, if the resistances of the resistors 2021 and 2022 are set to be high, the power is reduced. However, if the resistances of the resistors 2021 and 2022 are set to be high, the CR time constant of an input to the comparison circuit 203 increases, so that the response of the waveform of a signal input to the inverting input terminal (−) of the comparison circuit 203 is delayed. Further, referring to FIG. 7, the oscillator 204 performs an oscillating operation when the input signal to the comparison circuit 203 becomes equal to or less than the reference voltage Vref. However, when the response of the comparison circuit 203 is delayed, the oscillating operation of the oscillator 204 is also delayed. Accordingly, at the time of switchover from the standby state to a read operation, a reduction in the word line driving power supply potential caused by the operation of an activated word driver cannot be sufficiently coped with. Consequently, defective reading of data from a selected cell may also be brought about.
In order to maintain the word line driving power supply potential (which is also referred to as a “read time boosted potential”) when a transition from the standby state to the read operation is made, a configuration should be employed in which the reaction speed of the comparison circuit 203 in FIG. 7 is sped up. In this case, supply of electric charge that has been lost during the transition from the standby state to the read operation can be performed instantly. However, if the resistances of the resistors 2021 and 2022 are set to be low, current consumption at the time of a standby will be increased.
As a publication that has disclosed a technique related to the present invention which will be described later, a description in Patent Document 1 that has disclosed a configuration provided with two boost circuits is also referred to. In this Patent Document 1, the configuration is disclosed in which a semiconductor integrated circuit (which is a DRAM using a method of applying a boosted voltage to a word line) includes first and second boost circuits. The semiconductor integrated circuit supplies a boosted voltage that is used as a word line potential with stability even if a supply voltage has been reduced. The second boost circuit generates a second boosted voltage of Vpp+α, which is higher than a boosted voltage Vpp generated by the first boost circuit. The boosted voltage Vpp becomes the word line potential. In an electrostatic capacitor element, electric charge is stored. The semiconductor integrated circuit includes a comparison circuit for comparing the boosted voltage Vpp with a threshold value. When the voltage Vpp is reduced to be lower than the threshold value due to reduction in the power supply voltage Vcc, the comparison circuit outputs a control signal to a switching unit so that the electric charge stored in the electrostatic capacitor element are supplied as the voltage Vpp. In the configuration disclosed in this Patent Document 1, however, when the high voltage Vpp is reduced to be lower than the threshold value, switchover to the second boost circuit that generates Vpp+α is just performed. Incidentally, in the case of a flash memory, the boosted voltage or the gate voltage of the EEPROM of VPP+α will also become a factor for accelerating a read disturb (that induces software writing) in a read mode.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P-2000-268562 A (p3, FIG. 1)